| Bug | Description |
|---|
| CVE-2022-21166 | Incomplete cleanup in specific special register write operations for s ... |
| CVE-2022-21151 | Processor optimization removal or modification of security-critical co ... |
| CVE-2022-21127 | Incomplete cleanup in specific special register read operations for so ... |
| CVE-2022-21125 | Incomplete cleanup of microarchitectural fill buffers on some Intel(R) ... |
| CVE-2022-21123 | Incomplete cleanup of multi-core shared buffers for some Intel(R) Proc ... |
| CVE-2021-33120 | Out of bounds read under complex microarchitectural condition in memor ... |
| CVE-2021-33117 | Improper access control for some 3rd Generation Intel(R) Xeon(R) Scala ... |
| CVE-2021-0145 | Improper initialization of shared resources in some Intel(R) Processor ... |
| CVE-2021-0127 | Insufficient control flow management in some Intel(R) Processors may a ... |
| CVE-2020-24513 | Domain-bypass transient execution vulnerability in some Intel Atom(R) ... |
| CVE-2020-24512 | Observable timing discrepancy in some Intel(R) Processors may allow an ... |
| CVE-2020-24511 | Improper isolation of shared resources in some Intel(R) Processors may ... |
| CVE-2020-24489 | Incomplete cleanup in some Intel(R) VT-d products may allow an authent ... |
| CVE-2020-8698 | Improper isolation of shared resources in some Intel(R) Processors may ... |
| CVE-2020-8696 | Improper removal of sensitive information before storage or transfer i ... |
| CVE-2020-8695 | Observable discrepancy in the RAPL interface for some Intel(R) Process ... |
| CVE-2020-0549 | Cleanup errors in some data cache evictions for some Intel(R) Processo ... |
| CVE-2020-0548 | Cleanup errors in some Intel(R) Processors may allow an authenticated ... |
| CVE-2020-0543 | Incomplete cleanup from specific special register read operations in s ... |
| CVE-2019-14607 | Improper conditions check in multiple Intel® Processors may allow ... |
| CVE-2019-11139 | Improper conditions check in the voltage modulation interface for some ... |
| CVE-2019-11135 | TSX Asynchronous Abort condition on some CPUs utilizing speculative ex ... |
| CVE-2019-11091 | Microarchitectural Data Sampling Uncacheable Memory (MDSUM): Uncacheab ... |
| CVE-2018-12130 | Microarchitectural Fill Buffer Data Sampling (MFBDS): Fill buffers on ... |
| CVE-2018-12127 | Microarchitectural Load Port Data Sampling (MLPDS): Load ports on some ... |
| CVE-2018-12126 | Microarchitectural Store Buffer Data Sampling (MSBDS): Store buffers o ... |
| CVE-2018-3646 | Systems with microprocessors utilizing speculative execution and addre ... |
| CVE-2018-3640 | Systems with microprocessors utilizing speculative execution and that ... |
| CVE-2018-3639 | Systems with microprocessors utilizing speculative execution and specu ... |
| CVE-2018-3620 | Systems with microprocessors utilizing speculative execution and addre ... |
| CVE-2018-3615 | Systems with microprocessors utilizing speculative execution and Intel ... |
| CVE-2017-5715 | Systems with microprocessors utilizing speculative execution and indir ... |