| Bug | Description |
|---|
| CVE-2025-24495 | Incorrect initialization of resource in the branch prediction unit for ... |
| CVE-2025-20623 | Exposure of sensitive information caused by shared microarchitectural ... |
| CVE-2025-20103 | Insufficient resource pool in the core management mechanism for some I ... |
| CVE-2025-20054 | Uncaught exception in the core management mechanism for some Intel(R) ... |
| CVE-2025-20012 | Incorrect behavior order for some Intel(R) Core\u2122 Ultra Processors ... |
| CVE-2024-45332 | Exposure of sensitive information caused by shared microarchitectural ... |
| CVE-2024-43420 | Exposure of sensitive information caused by shared microarchitectural ... |
| CVE-2024-39355 | Improper handling of physical or environmental conditions in some Inte ... |
| CVE-2024-39279 | Insufficient granularity of access control in UEFI firmware in some In ... |
| CVE-2024-37020 | Sequence of processor instructions leads to unexpected behavior in the ... |
| CVE-2024-36293 | Improper access control in the EDECCSSA user leaf function for some In ... |
| CVE-2024-31157 | Improper initialization in UEFI firmware OutOfBandXML module in some I ... |
| CVE-2024-31068 | Improper Finite State Machines (FSMs) in Hardware Logic for some Intel ... |
| CVE-2024-29214 | Improper input validation in UEFI firmware CseVariableStorageSmm for s ... |
| CVE-2024-28956 | Exposure of Sensitive Information in Shared Microarchitectural Structu ... |
| CVE-2024-28127 | Improper input validation in UEFI firmware for some Intel(R) Processor ... |
| CVE-2024-28047 | Improper input validation in UEFI firmware for some Intel(R) Processor ... |
| CVE-2024-25939 | Mirrored regions with different values in 3rd Generation Intel(R) Xeon ... |
| CVE-2024-24980 | Protection mechanism failure in some 3rd, 4th, and 5th Generation Inte ... |
| CVE-2024-24968 | Improper finite state machines (FSMs) in hardware logic in some Intel( ... |
| CVE-2024-24853 | Incorrect behavior order in transition between executive monitor and S ... |
| CVE-2024-24582 | Improper input validation in XmlCli feature for UEFI firmware for some ... |
| CVE-2024-23984 | Observable discrepancy in RAPL interface for some Intel(R) Processors ... |
| CVE-2024-23918 | Improper conditions check in some Intel(R) Xeon(R) processor memory co ... |
| CVE-2024-21853 | Improper finite state machines (FSMs) in the hardware logic in some 4t ... |
| CVE-2024-21820 | Incorrect default permissions in some Intel(R) Xeon(R) processor memor ... |
| CVE-2023-49141 | Improper isolation in some Intel(R) Processors stream cache mechanism ... |
| CVE-2023-47855 | Improper input validation in some Intel(R) TDX module software before ... |
| CVE-2023-46103 | Sequence of processor instructions leads to unexpected behavior in Int ... |
| CVE-2023-45745 | Improper input validation in some Intel(R) TDX module software before ... |
| CVE-2023-45733 | Hardware logic contains race conditions in some Intel(R) Processors ma ... |
| CVE-2023-43758 | Improper input validation in UEFI firmware for some Intel(R) processor ... |
| CVE-2023-43490 | Incorrect calculation in microcode keying mechanism for some Intel(R) ... |
| CVE-2023-42667 | Improper isolation in the Intel(R) Core(TM) Ultra Processor stream cac ... |
| CVE-2023-39368 | Protection mechanism failure of bus lock regulator for some Intel(R) P ... |
| CVE-2023-38575 | Non-transparent sharing of return predictor targets between contexts i ... |
| CVE-2023-34440 | Improper input validation in UEFI firmware for some Intel(R) Processor ... |
| CVE-2023-28746 | Information exposure through microarchitectural state after transient ... |
| CVE-2023-23908 | Improper access control in some 3rd Generation Intel(R) Xeon(R) Scalab ... |
| CVE-2023-23583 | Sequence of processor instructions leads to unexpected behavior for so ... |
| CVE-2023-22655 | Protection mechanism failure in some 3rd and 4th Generation Intel(R) X ... |
| CVE-2022-41804 | Unauthorized error injection in Intel(R) SGX or Intel(R) TDX for some ... |
| CVE-2022-40982 | Information exposure through microarchitectural state after transient ... |
| CVE-2022-38090 | Improper isolation of shared resources in some Intel(R) Processors whe ... |
| CVE-2022-33972 | Incorrect calculation in microcode keying mechanism for some 3rd Gener ... |
| CVE-2022-33196 | Incorrect default permissions in some memory controller configurations ... |
| CVE-2022-21233 | Improper isolation of shared resources in some Intel(R) Processors may ... |
| CVE-2022-21216 | Insufficient granularity of access control in out-of-band management i ... |
| CVE-2022-21166 | Incomplete cleanup in specific special register write operations for s ... |
| CVE-2022-21151 | Processor optimization removal or modification of security-critical co ... |
| CVE-2022-21127 | Incomplete cleanup in specific special register read operations for so ... |
| CVE-2022-21125 | Incomplete cleanup of microarchitectural fill buffers on some Intel(R) ... |
| CVE-2022-21123 | Incomplete cleanup of multi-core shared buffers for some Intel(R) Proc ... |
| CVE-2021-33120 | Out of bounds read under complex microarchitectural condition in memor ... |
| CVE-2021-33117 | Improper access control for some 3rd Generation Intel(R) Xeon(R) Scala ... |
| CVE-2021-0145 | Improper initialization of shared resources in some Intel(R) Processor ... |
| CVE-2021-0127 | Insufficient control flow management in some Intel(R) Processors may a ... |
| CVE-2020-24513 | Domain-bypass transient execution vulnerability in some Intel Atom(R) ... |
| CVE-2020-24512 | Observable timing discrepancy in some Intel(R) Processors may allow an ... |
| CVE-2020-24511 | Improper isolation of shared resources in some Intel(R) Processors may ... |
| CVE-2020-24489 | Incomplete cleanup in some Intel(R) VT-d products may allow an authent ... |
| CVE-2020-8698 | Improper isolation of shared resources in some Intel(R) Processors may ... |
| CVE-2020-8696 | Improper removal of sensitive information before storage or transfer i ... |
| CVE-2020-8695 | Observable discrepancy in the RAPL interface for some Intel(R) Process ... |
| CVE-2020-0549 | Cleanup errors in some data cache evictions for some Intel(R) Processo ... |
| CVE-2020-0548 | Cleanup errors in some Intel(R) Processors may allow an authenticated ... |
| CVE-2020-0543 | Incomplete cleanup from specific special register read operations in s ... |
| CVE-2019-14607 | Improper conditions check in multiple Intel\xae Processors may allow a ... |
| CVE-2019-11139 | Improper conditions check in the voltage modulation interface for some ... |
| CVE-2019-11135 | TSX Asynchronous Abort condition on some CPUs utilizing speculative ex ... |
| CVE-2019-11091 | Microarchitectural Data Sampling Uncacheable Memory (MDSUM): Uncacheab ... |
| CVE-2018-12130 | Microarchitectural Fill Buffer Data Sampling (MFBDS): Fill buffers on ... |
| CVE-2018-12127 | Microarchitectural Load Port Data Sampling (MLPDS): Load ports on some ... |
| CVE-2018-12126 | Microarchitectural Store Buffer Data Sampling (MSBDS): Store buffers o ... |
| CVE-2018-3646 | Systems with microprocessors utilizing speculative execution and addre ... |
| CVE-2018-3640 | Systems with microprocessors utilizing speculative execution and that ... |
| CVE-2018-3639 | Systems with microprocessors utilizing speculative execution and specu ... |
| CVE-2018-3620 | Systems with microprocessors utilizing speculative execution and addre ... |
| CVE-2018-3615 | Systems with microprocessors utilizing speculative execution and Intel ... |
| CVE-2017-5715 | Systems with microprocessors utilizing speculative execution and indir ... |